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Sr. Staff Design for Test Engineer

Location: San Jose, CA, United States
Date Posted:

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Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go.

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics and video processing, combined with world class software and silicon development.

Synaptics is looking for a Senior Staff Design for Test Engineer to join our dynamic and growing organization. You will be responsible for driving DFT architecture and the implementation of MBIST, SCAN, and BSCAN for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications. This position reports to the Senior Director, ASIC Design.

The typical base pay range for this position is USD $137,000 - $215,600 per year. Individual pay is determined by many factors including work location, job-related skills, experience, and relevant education or training. This position is also eligible for a discretionary annual performance bonus, equity, and other benefits. Note that compensation listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Job Duties

  • Develop DFT architecture and the implementation of MBIST, SCAN, and BSCAN for multi-million gate SoCs targeted for Voice Assistant & Multimedia applications
  • Collaborate with other team members to drive DFT methodology and flow to make it more efficient
  • Responsible for pre-silicon validation for all the DFT logic in block/full-chip
  • Synthesize / optimize the DFT logic for best PPA
  • Responsible for the Static Timing Closure for all the test logic in block/full-chip
  • Work with Test Engineering to bring-up/validate test patterns on ATE


  • Deep understanding of DFT architecture and methodologies
  • Excellent communication, interpersonal and analytical skills, including the ability to communicate complex, interactive design concepts clearly
  • Ability to work with dynamic, geographically distributed teams, with the passion to become part of cross-functional teams as necessary to ensure testability
  • Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance
  • Well organized with strong attention to detail; proactively ensures work is accurate
  • Positive attitude and work ethic; unafraid to ask questions and explore new ideas
  • Resourceful and able to solve complex problems through adaptation of existing technology and investigation of new technology to resolve complex problems


  • Bachelors (or masters) degree in Electrical Engineering or related field or equivalent
  • 12+ years of experience
  • Hands on expertise with DFT architecture DFT planning for complex multi-million gate SoCs.
  • Hands on expertise with Scan/EDT, MBIST, and Boundary Scan for complex multi-million gate SoCs in cutting edge process nodes.
  • Experience in creating iJTAG structure in Verilog
  • Experience with deep debug through waveform
  • Direct experience using PERL scripting to create and maintain EDA tool flows
  • Experience with Logic Synthesis and Static Timing Closure is a strong plus
  • Working knowledge of Tessent tool flow is a strong plus
  • No travel required

Belief in Diversity
Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.