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Staff IC Layout Design Engineer

Location: Bangalore, India
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Description

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go. 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development. 

Overview 

Synaptics is looking for a Staff IC Layout Design Engineer to join our dynamic and growing organization. The ideal candidate will work closely with circuit design and cross-functional teams, leading, planning, and executing IP layouts, while also mentoring and coaching junior engineers. This position reports to the Sr. Manager, IC Layout. 

Responsibilities & Competencies 

Job Duties

  • Layout design, planning and development of Critical Analog, Mixed Signal Macros and High-Speed IO Protocols and IO ring layouts 
  • Perform compact Macro layout including hierarchical modules floorplan, power and signal routing, physical verification, quality check and timely documentation 
  • Deliver quality layout on-schedule meeting design intent including Speed, Capacitance, Resistance, Power, Noise, and Area 
  • Plan and complete assignments independently by understanding customer requirements, identify issues that impact customer satisfaction, and provide solutions to mitigate impacts 
  • Collaborate effectively work with co-workers and partner closely with global circuit design and CAD engineering teams to achieve goals and solve problems 

Competencies

  • Good understanding of active and passive devices, circuits and electrical fundamentals 
  • Familiar with CMOS, FDSOI and FinFET fabrication concepts, Deep Nwell and triple well process
  • Must have knowledge of analog layout techniques, electromigration, ESD, latch up, crosstalk, shielding and deep sub-micron challenges
  • Familiar with DEF & LEF creation
  • Familiar with EMIR checks and fixes
  • Good analytical, debug and problem-solving skills in resolving layout design challenges and physical verification issues
  • Resourceful and able to solve complex problems through adapting technology and a solid understanding of product architecture 
  • Proactive, self-starter, able to work independently and as a lead in a fast-paced environment
  • Well organized with strong attention to detail; proactively ensures work is accurate
  • Positive attitude and work ethic; unafraid to ask questions and explore new ideas
  • Good verbal, and written communication skills with the flexibility to excel within a diverse, cross functional and multi-site team environment, spanning different time zones

Qualifications (Requirements) 

  • Bachelor’s or Master’s degree in Electrical Engineering, ECE, EEE or related field, or equivalent 
  • 8+ years of full custom Layout experience 
  • Demonstrated ability to lead projects from inception through completion 
  • Proficient with scripting Languages (CSH, Perl, Skill, TCL, PYTHON, etc.) to improve layout efficiency and workflow
  • Hands-on experience with Virtuoso L/XL/GXL (6.1.x and 12.1.x), Calibre, PERC and STARRC tools
  • Hands-on experience on Flipchip/wirebond schemes is a plus 
  • Experience with RF layout is an additional plus
  • No travel required 

  

Belief in Diversity

Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information. 

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