Join our Talent Network
Skip to main content

Sr. Staff Digital Engineer, Synthesis and STA

Location: Bangalore, India
Date Posted:

Share:
Save Job Saved

Description

Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go. 

We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development. 

Overview 

Synaptics is looking for a Sr. Staff Digital Engineer, Synthesis and STA to join our dynamic and growing WPD organization. You will be responsible for Synthesis, Static Timing Analysis and signoff methodologies of WLAN-SoC and its subsystem for the Wi-Fi 6/7 product targeted for IoT market. You shall leverage your technical expertise in the synthesis, STA and Timing ECOs methodologies for quality signoff and Tape out. This position reports to the VP, Silicon Engineering 

Responsibilities & Competencies 

Job Duties

  • Define synthesis methodologies, execute the synthesis flow and generate the netlist meeting the PPA goals along with the equivalence and low power check  
  • Develop clocking and constraints development for functional and DFT modes  
  • Conduct Static Timing Analysis and implement signoff methodologies for WLAN-SOC  
  • Perform post silicon timing debug activityand improve the signoff environment and methodologies  
  • Execute Timing ECOs, leakage recovery, chip power analysis using PTPX  
  • Collaborate closely with design / DFT team and explore the opportunity to improve the PPA targets 

Competencies

  • Strong Digital design fundamentals
  • Deep understanding of design compiler, formality, prime time, tweaker EDA tool sets
  • Low power design concept and well versed in UPF
  • Advance technology node experience and its associated challenges
  • Knowledge in Lint, CDC, timing constraints, synthesis, power analysis
  • Good scripting Skills (Tcl/Python/Perl)
  • Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance
  • Organized with strong attention to detail; proactively ensures work is accurate
  • Positive attitude and work ethic; unafraid to ask questions and explore new ideas
  • Analytical and able to make informed decisions based on experience
  • Sets clear expectations and objectives, and brings parties together to drive key initiatives
  • Ability to work within a diverse team and mentor developing team members 
  • Excellent verbal and written communication 

Qualifications (Requirements) 

  • Bachelor's or Master's degree in Computer Engineering, Communication, Electrical/Electronic Engineering or related field or equivalent 
  • 12+ years of experience in synthesis, STA and Timing ECO cycle  
  • Experience with tape out of new product 
  • No travel required 

    

Belief in Diversity

Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.

Share: