Principal Digital Engineer, PCIE Subsystems
Location: Bangalore, India
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Description
Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions.
We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.
Overview
Synaptics is looking for a PCIE Subsystem design lead to join our dynamic and growing Wireless Products Division (WPD) ASIC team. You will design & own PCIe subsystems and participate in various other aspects of WPD SoCs (analog IP/Serdes integration, clocking, reset, error handling, debug, chip management etc.). You will also drive verification activities for PCIe Subsystems and SOC integration, support emulation, and post silicon debug. This is a highly cross-functional role that will require coordination and co-design with our software and system hardware counterparts. This position reports to the Director, Digital Engineering.
Responsibilities & Competencies
Job Duties
- Own a technical leadership role in architecting area and power efficient low latency designs with scalabilities and flexibilities driving innovation in low power design and performance enhancement
- Work mostly independently to create and review PCIe subsystem's design microarchitecture specifications
- Collaborate with SoC Architects in performance analysis and propose IP enhancements or any new IP requirement in the SOC
- Develop RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work on interfacing with Analog (Serdes) IP, clocking and reset architecture for PCIe subsystem and integration with SoC
- Work with Design Validation (DV) teams to create test plans to verify and debug design RTL
- Partner with physical design teams to ensure designs meet physical requirements and timing closure
- Support chip bring-up, debug, and transforming from first sample through release to volume production
- Provide technical guidance for Corrective & Preventive Action planning and tracking
Competencies
- Deep domain knowledge of PCIe System Architecture (PIPE,TL and PMA)
- Strong understanding of chip bus interconnects specially AXI/ACE/AHB/APB. Understanding of other highspeed interconnects, CPU architecture is a plus
- Strong understanding of the SOC development flow and low power design
- Knowledge in Lint, CDC, timing constraints, synthesis, STA, power analysis
- Ability to communicate complex, interactive design concepts clearly
- Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance
- Well organized with strong attention to detail; proactively ensures work is accurate
- Positive attitude and work ethic; unafraid to ask questions and explore new ideas
- Resourceful and able to solve highly complex problems through adaptation of existing technology and development of new technology with a deep understanding of product architecture
- Should possess strong communication and leadership skills to ensure effective communication with Program Management or Engineering Management and group members
- Ability to work within a diverse team and mentor developing team members
Qualifications (Requirements)
- Bachelor’s (or master’s) degree in Computer Engineering, Communication, Electrical/Electronic Engineering or related field, or equivalent
- 15+ years of experience in the design and delivery of Ips, Subsystems, and SOCs with minimum 5 years of experience in handling PCIe Subsystems
- Experience in supporting emulation platforms, PCIe silicon bring up, and SW team support
- Experience defining and using advanced front-end design flows based on industry standard EDA tools from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team
- No travel required
Belief in Diversity
Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.
Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.
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